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LPC1517JBD48E LPC824M201JHI33E
第一枪帮您来“拼单”，更多低价等你来！LPC1517JBD48E LPC824M201JHI33E
- 名称深圳市斯瑞特科技有限公司 【公司网站】
- 所在地中国 广东 深圳
- 联系人 朱小姐
- 价格 ￥6.3元/件 点此议价
- 采购量 不限制
- 发布日期 2020-09-23 13:50 至 长期有效
热线：13560767759
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LPC1517JBD48E LPC824M201JHI33E产品详情
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- BGA-100:BGA-100
- 品牌:TI/德州仪器
- 封装形式:DIP
- 类型:数字集成电路
- 用途:军工
- 功能:单片机
- 导电类型:双极型
- 封装外形:金属壳圆形型
- 集成度:小规模(<50)
- 型号:BGA-100
- 批号:2017+
• <*n class="ft6">An entire port value can be written in one instruction.
• <*n class="ft6">Mask, set, and clear operati* are supported for the entire port.
All GPIO port pins are fixed-pin functi* that are enabled or disabled on the pins by the
switch matrix. Therefore each GPIO port pin is assigned to one specific pin and cannot be
moved to another pin. Except for pins SWDIO/PIO0_2, SWCLK/PIO0_3, and
RESET/PIO0_5, the switch matrix enables the GPIO port pin function by default.
8.10.1 Features
• <*n class="ft6">Bit level port registers allow a single instructio*set and clear any number of bits in
one write operation.
• <*n class="ft6">Direction co*ol of individual bits.
• <*n class="ft6">All I/O default to inputs with internal pull-up resistors enabled after reset - except for
the I2<*n class="ft6">C-bus true open-drain pins PIO0_2 and PIO0_3.
• <*n class="ft6">Pull-up/pull-down configuration, repeater, and open-drain modes can be programmed
through the IOCON block for each GPIO pin (see Figure 7).
• <*n class="ft6">Co*ol of the digital output slew rate allowing to switch more outputs simultaneously
withou*gr*g the power/ground distribution of the device.
8.11 Pin interrupt/pattern match engine
The pin interrupt block configures up to eight pins from all digital pins for providing eight
external interrupts connected to the NVIC.
The pattern match engine can be used, in conjunction with software, to create complex
state machines based on pin inputs.
Any digital pin, independently of the functi*elected through the switch matrix, can be
configured through the SYSCON block as input to the pin interrupt or pattern match
engine. The registers that co*ol the pin interrupt or pattern match engine are located on
the IO+ bus for fast single-cycle access.
8.11.1 Features
• <*n class="ft6">Pin interrupts
– Up to eight pins can be selected from all digital pins as edge- or level-sensitive
interrupt requests. Each request creates a separate interrupt in the NVIC.
– Edge-sensitive interrupt pins can interrupt on rising or falling edges or both.
– Level-sensitive interrupt pins can be HIGH- or LOW-active.
– Pin interrupts can wake up the LPC81xM from sleep mode, deep-sleep mode, and
deep power-down mode.
• <*n class="ft6">Pin interrupt pattern match engine
– Up to 8 pins can be selected from all digital pins to co*ibute to a boolean
expression. The boolean expression c*ists of specified levels and/or transiti*
on various combinati* of these pins.
– Each minters (product term) comprising the specified boolean expression can
generate its own, dedicated interrupt request
以上内容为LPC1517JBD48E LPC824M201JHI33E，本产品由深圳市斯瑞特科技有限公司直销供应。
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